The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to the cointegration of vertical field effect transistors (VFETs) having III-V channel material with VFETs having germanium (Ge) channels material on the same substrate.
Semiconductor devices are typically formed using active regions of a wafer. In an integrated circuit (IC) having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by incorporating n-type or p-type impurities in the layer of semiconductor material. A conventional geometry for MOSTFETs is known as a planar device geometry in which the various parts of the MOSFET device are laid down as planes or layers.
A type of MOSFET is a non-planar FET known generally as a vertical field effect transistor (VFET). VFETs employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density and some increased performance over lateral devices. In VFETs the source to drain current flows in a direction that is perpendicular to a major surface of the substrate. For example, in a known VFET configuration a major substrate surface is horizontal and a vertical fin extends upward from the substrate surface. The fin forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while a gate is disposed on one or more of the fin sidewalls. As silicon CMOS (complementary metal oxide semiconductor) technology reaches fundamental scaling limits, alternative materials such as high mobility III-V compounds and Ge have proven to be contenders for extending high performance logic devices.